The centerpiece of the HP2C project will be approximately ten high-risk/high-payoff software development projects for supercomputing applications that will run at scale on the next generation of computers in 2012/13, when the large petascale computing platform of the HPCN Initiative will be installed at the Swiss National Supercomputing Center (CSCS) in Ticino. It is anticipated that one or more HPC software developers will be funded per project at Universities or EPFL for up to three years, and that these people will be embedded in domain science teams that are developing computational science software for simulations at scale. These embedded software developers, as well as other members of the domain science teams, are expected to be in close contact with the core group of scientific computing experts at CSCS and USI through frequent site visits to the Lugano area. The resulting interdisciplinary teams should engage research and development activities that include:

1. First and foremost, teams should engage in research and application development targeted at problems or classes of problems that require several orders of magnitude more computer performance than the domain science groups would be able to investigate with current hardware and software systems.
2. Teams should engage in new developments or significant refactoring of application codes. Software development should proceed in stages with clearly defined milestones for testing and validation. The development should lead to a significant leap forward in simulation capabilities. Incremental developments based on current simulation software are not encouraged.
3. Emerging parallel programming models should be investigated and employed, such as: hybrid approaches with two or more levels of parallelism such as distributed memory and shared memory (e.g. MPI/OpenMP or MPI/pthread); use of partitioned global address space (PGAS) languages such as Unified Parallel C, Fortran with co-arrays, or Global Arrays; new DARPA HPCS languages such as Chapel or X10; programming models for heterogeneous platforms consisting of a few fast, low-latency cores, and a larger number high-throughput cores.
4. It is expected that teams engage in significant algorithmic developments in order to adequately cope with abovementioned brutal facts of HPC (scaling, memory issues, and fault tolerance/resilience). This might include reconsidering the workflow, in particular where I/O at scale might become a bottleneck and has to be reduced or eliminated in order to bring down demands on the I/O sub-system.
5. Teams are encouraged to consider heterogeneous architectures, such as the use of Graphic Processing Units (GPU) and Cell Broadband Engine in combination with or as alternative to the mainstream multicore processor technologies.

Teams are encouraged to develop open source software.